Main Navigation Home C++ Basics CS Fundamentals Low Latency C++

Appearance

Sidebar Navigation

CPU Architecture Basics

Bitwise Operations

Binary Representation of Types

Byte Order and Endianness

CPU Registers and Assembly Instructions

CPU Cache Hierarchy and Prefetching

Pipelined Processors and Instruction Execution

Odd one out!

CPU Architecture Advanced

Branch Prediction

Advanced Cache Analysis and Optimization

Instruction Reordering and Out-of-Order Execution

Vectorization, SIMD, and AVX-512

NUMA Architecture

Operating Systems

Process vs Threads

Process Memory Model

Virtual Memory Management

Process Creation and Lifecycle

Kernel and OS Architecture

Context Switching and System Calls

Process Scheduling

OS-Level Synchronization Primitives

Deadlocks, Starvation, and Livelocks

Programming Principles

Algorithmic Complexity

Compiler Optimizations

Memory Management Fundamentals

Garbage Collection Techniques

Object-Oriented Design Principles

Networks

TCP/IP Model Overview

Network Access Layer

Internet Layer

Transport Layer

UDP Protocol

TCP Protocol

IPC

TCP/UDP System Calls

Pipes and Message Queues

Memory-Mapped Files (mmap)

POSIX Shared Memory

IPC Trade-offs and Performance

Zero-Copy Techniques

Lock-Free IPC Patterns

Userspace Networking

Zero-Copy Networking

Polling vs Interrupts

Kernel Bypass Techniques: DPDK, RDMA, Solarflare/OpenOnload

On this page

CPU Architecture Advanced

Branch Prediction
Advanced Cache Analysis and Optimization
Instruction Reordering and Out-of-Order Execution
Vectorization, SIMD, and AVX-512
NUMA Architecture

Pager

Next pageBitwise Operations

Mark as complete

CPU Architecture Advanced ​

CPU Architecture Advanced